The present invention relates generally to the data processing field, and more particularly, relates to a method and apparatus for implementing enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures.
During manufacture of integrated circuits, manufacturers rely on sophisticated testers to test the chips via external pins. Test stimulus are applied via external pins to the inputs and the outputs are observed. Typical manufacturing defects include shorts, opens, stuck-at-1, stuck-at-0, and the like. As integrated circuit technology improves, more and more logic can be packed into a single package or chip. Single chip microprocessors, as an example, include millions of transistors including multiple memory arrays and logic. A limited number of pins exist on a chip package and the number of pins a tester can handle is limited. Typically some hardware for testing is provided on the IC chip. On-chip testing hardware is used to test the chip, such as, a built-in self-test (BIST) hardware.
Logic built-in self-test (LBIST) in the industry is primarily used for detecting stuck at faults. In this case, isolation to the single failing latch is fairly straight forward. The simplest method being a binary search to locate the first failing cycle, during which a failing result indicates that the failing test is earlier in the sequences, while a passing result says it is later. Once the first failing cycle is located the scan rings are dumped and compared against known good results.
Known designs not only incorporate at speed testing into LBIST, but commonly use this function in conjunction with clock skewing to track hardware performance and potentially sort chips. As a result, occurrence of intermittent failures becomes more common. Analysis of these intermittent failures is more problematic. During the same binary search, a failing result continues to indicate that the failure is earlier in the test, while a passing result may indicate the failure is later, or simply that it did not occur this time. It is not usually possible to be sure which cycle is actually failing, until extra effort is taken in analyzing all scan channel latches.
A need exists for an improved mechanism for implementing diagnostics of intermittent failures.
A principal object of the present invention is to provide a method and apparatus for implementing enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures. Other important objects of the present invention are to provide such method and apparatus for enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, a method and apparatus are provided for enhanced Logic Built in Self Test (LBIST) diagnostics of intermittent failures. A respective one of a plurality of first multiplexers is coupled between adjacent sequential channels of a plurality of sequential channels under test. Each of the first multiplexers selectively receives a first data input in a first scan mode with the sequential channels configured in a common scan path and a second data input in a second scan mode with each the sequential channels configured in a separate scan path responsive to a first control signal. A second multiplexer, coupled between a test data output of a last sequential channel and the first data input of a first sequential channel; selectively receives the test data output of the last sequential channel and an external test data input responsive to a recirculate control signal. A first multiple input signature register (MISR) including multiple MISR inputs is coupled to a respective one of the plurality of sequential channels under test. A blocker function is coupled between the first multiple input signature register and the plurality of sequential channels under test. The blocker function is configured for blocking all MISR inputs except for a single MISR input receiving the test data output of the last sequential channel responsive to the recirculate control signal. A second MISR shadow register is coupled to the first multiple input signature register.
In accordance with features of the invention, the examination of at least two successive LBIST cycles is enabled so that intermittently failing test cycles can be easily located. The second MISR shadow register stores MISR data for comparison with MISR data from the first multiple input signature register. A plurality of secondary MISR shadow registers with an associated cycle count register can be used for storing MISR data for comparison with MISR data from the first multiple input signature register with a matching cycle count.